PScan2™ System Architecture
From the ground up, the PScan2™ controller was designed for maximum flexibility. Because of its unique design, the PScan2™ controller offers high performance combined with high value. A few of the advanced features of the PScan2™ controller are:  PScan2™ Controller Block Diagram Master-Slave Design:
Communication between the master computer and the slave controller is through an industry standard Ethernet communications protocol and incorporates a Data-Command Exchange (DCExT) protocol for information transfer. Thus, the master computer may be PC, MAC or UNIX based. A PC Windows™ XP version of the master software is shipped with every unit. Furthermore, a single master unit can be used with many slaves. Proprietary Pacific Nanotechnology software permits real time control of parameters, including PID settings, scan range and scan speed. Microprocessor Based Controller:
The sophisticated PScan2™ electronic controller is based on a Pentium CPU and operates independently of the master computer. The controller has its own RAM, and a 2+ gigabyte hard drive for storing a high quantity of data. The high speed communications protocol allows the simultaneous X-Y positioning and acquisition of up to three high resolution images (1024 x 1024) at 20 kHz or four images at 16 kHz. Flexibility:
Many types of Probe Microscope heads are easily controlled by the PScan2™. As an example, support is provided for tripod and tube scanners having external linearizers. Probe approach is achieved by stepping and DC motors. The controller comes standard with three high voltage amplifiers and with the high voltage upgrade board. Another five high voltage amplifiers can be added. Expandable:
The PScan2™ is the first ever control system designed for the direct control of more than one SPM head using a single master computer. Using the Ethernet connection, multiple heads may be controlled simultaneously. Many new types of scientific and inspection applications are possible for the first time with the PScan2™ controller. For example, this architecture enables arrayed SPM design which is needed for next generation of quality control tools in semiconductor manufacturing.
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